What's a current conveyor?

Theory

Just as the opamp is a basic signal processing block for 'voltage mode' signal processing, the current conveyor is the equivalent for 'current mode'.

The CCII+ is a specific version of a current conveyor. It is a three terminal device (X,Y,Z) for which the relationship between the terminals can be defined in matrix form as,

$$\begin{bmatrix} i_y \\ v_x \\ i_z \end{bmatrix} = \begin{bmatrix} 0 & 0 & 0\\ 1 & 0 & 0\\ 0 & 1 & 0 \end{bmatrix} \begin{bmatrix} v_y \\ i_x \\ v_z \end{bmatrix}$$

From this relationship one sees that the current into Y is zero. The voltage applied to Y is seen at X, and the current that flows as a result from X is mirrored at the output Z. With some intuition, this can be related to a voltage follower circuit between Y and X, for which the output stage is part of a current mirror circuit to Z.

Why make a new one?

Current conveyors are not new and are well-understood in the literature. They are used in high speed signal processing designs due to higher achievable bandwidth with current mode processing.

At university, we were introduced to this device for analogue signal processing, but upon trying to buy myself one to play with (quick DigiKey search as is customary), I found that no such products were available.

PCB Design

Schematic

In order to accurately mirror the current from X to Z, the device requires good matching between the characteristics of the transistors on each side of the mirror. For a BJT design, this requires that the $\beta$ value and $V_{BE}$ matching is good, such that two devices with the same $V_{BE}$ will source approximately the same current through the collector. A similar logic is applied with matching MOSFETs.

In my work, I had stumbled across some interesting products from Nexperia, featuring matched BJTs in a single package such as the BCM847. These will provide sufficient matching for this prototype design. The schematic, captured in KiCad, for the discrete CCII+ is shown below.

Features of note in this schematic include:

1. The output drive to X is directly from the output stage of an opamp! The current consumption from the supply rails is mirrored.
2. Wilson current mirrors have been used to provide the Z output.

Driving X direct from the LM7321 was a eureka moment, whilst playing in QSPICE with the design. Discrete implementation I had seen in my education implemented a push-pull stage outside the opamp, which was mirrored onto Z. The implementation seen here saves at least 2 devices by recognising that the push-pull stage is already implemented inside the opamp output stage and that the quiescent supply through U1 will flow through both mirrors and be cancelled at Z. Thinking this was very creative, I looked to see if anyone had in fact published this design and of course this exact circuit is shown in a figure from 40 years ago by a legend of the field (at least it means this isn't a silly approach),

Two new circuit approaches have been described, previously used for current convertors, to produce versatile precision CCII+ current conveyors suitable for monolithic fabrication. The performance of the discrete implementation offers a significant improvement over previous conveyor designs.

• HIGH-PERFORMANCE CURRENT CONVEYOR IMPLEMENTATION B. Wilson 17th October 1984

Whilst simulating the DC current error performance with single transistor current mirrors, poor behaviour was observed with varying output voltage. This was of course due to 'early effect' of the BJTs, or rather in analogue design terminology a finite output impedance of the mirror.

$$I_C = I_S e^{\frac{V_{BE}}{V_T}}(1 + \frac{V_{CE}}{V_A})$$

As seen above, the current through a BJT is not only dependent on the $V_{BE}$ voltage, but also the voltage at the collector, which is undesirable for our CCII+ design as we wish the current out of Z to be independent of the voltage applied to the load on Z.

Implementing a four-transistor Wilson current mirror mitigates this problem by increasing the output impedance. With all engineering, no free lunch is had, and the additional transistor $V_{BE}$ drops limit the output voltage swings achievable at X and Z, requiring larger supply voltages for the device. This design is really intended for something like +-12V rails in an audio signal processing design.

Layout

Wanting this design to be useful for low frequency (i.e. audio) analogue prototypes on a breadboard, the layout is designed with 0.1inch pin header in mind. To fit all the devices onto a tiny little board, the QFN package versions of the Nexperia BJTs were selected.

The Rev A was manufactured with JLCPCB in a 2-layer standard process, 0.8mm board thickness.

Hand Assembly

With a steel stencil produced by JLCPCB, I threw together a little jig and scraped some Chip Quik paste onto a board. Very quickly it became apparent that the apertures for the BJT pads were so small that paste was blocking holes or not adhering to the pads as the stencil was removed.

I dramatically overestimated my ability to solder the BJTs and began soaking boards with flux in desperation.

Regardless, 2 boards were laboriously produced on a USB PD hot plate.

Testing

Quick breadboard bench testing with an oscilloscope, dual channel benchtop PSU and signal generator provides some incite into the circuit's behaviour and performance metrics.

Standard through-hole resistors were chosen and applied to the device as per the below image. $R_{X}$ and $R_{Z}$ were measured to be 429.0 and 219.3 Ohms respectively. This should provide a theoretical voltage ratio of 1.956 between X an Z, as per the assumption the currents in each branch are equal.

By application of a 1Vpp and 20Vpp square wave at Y with frequency 50mHz, one can measure the accuracy of the DC current in branches X and Z. The below table shows the measured voltages at X and Z for different applied input voltages, the ratio and deviation from the calculated value of 1.956.

Device 1

Input Voltage (V)	$v_{X}$	$v_{Y}$	r = $v_{X}$/$v_{Y}$	Percent Error (100r/1.956-100)
0.5	0.4974	0.25314	1.964920597	0.4560632565
-0.5	-0.4971	-0.24354	2.041143139	4.352921202
10	9.964	5.018	1.985651654	1.515933233
-10	-9.97	-4.849	2.05609404	5.117282209

Device 2

Input Voltage (V)	$v_{X}$	$v_{Y}$	r = $v_{X}$/$v_{Y}$	Percent Error (100r/1.956-100)
0.5	0.4965	0.2477	2.004440856	2.476526374
-0.5	-0.498	-0.2505	1.988023952	1.637216365
10	9.963	4.953	2.011508177	2.837841353
-10	-9.967	-5.07	1.965877712	0.5049955026

AC Transfer Function

One of the main applications for current conveyors in industry is the design of high frequency circuits due to the higher bandwidth properties of a current mode device without a bandwidth limited feedback network.

Sadly, due to the use of an opamp in this design, we observe a bandwidth limit at around 400kHz when distortion of the voltage at X begins to occur due to the slew rate limit of the LM7321 used as the unity gain buffer. This can be observed in the following graph.

It is noted in the above data that the ratio of the voltages at X and Z remains relatively constant despite the voltage distortion occuring at X. As expected, the current mirror stages are not struggling at higher frequencies.

Going to lower voltage inputs we can then observe new behaviour. The voltage distortion at X occurs at a much higher frequency in the MHz, as with a smaller peak to peak voltage swing the slew rate limit of the opamp is less significant. As the voltage begins to droop, the voltage at Z becomes very close to 0. We then see a sudden increase in the calculated ratio which is not as prominent in the higher voltage test. This is likely a form of cross-over distortion as seen in class-B and class-AB amplifiers, and is reduced by applying a DC offset to the input voltage.